Phase locked system design and measurement tutorial consisting of physical hardware and co-simulation environment

International Journal of Electrical Engineering Education,  Oct 2004  by Burbidge, Martin John

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Simulation response example for transfer function monitoring

The simulation model in Fig. 4 is used to emulate the circuit set-up outlined in the transfer function measurement practical module. The course notes recommend that the students have a copy of the respective lab notes for reference purposes.

The simulation model is initially set up to have a division ratio of 40 and a nominal reference frequency of 50kHz that is sinusoidally modulated at 580Hz. The modulation frequency is altered by double-clicking on the voltage source on the left-hand side of the circuit and changing the frequency parameter. These settings can be verified by inspection of the simulation model. The voltage source and U2 on the far left of the schematic emulates the signal generation circuitry used in the associated lab session. The modulation frequency is chosen to match the natural frequency estimated from the component values. The output of the PLL should have its greatest magnitude response at this frequency. The course material contains the full simulation model shown in Fig. 4 and instructions are provided to carry out the simulation with the parameters mentioned. After the simulation is complete the response plot illustrated in Fig. 5 is displayed.

In Fig. 5 the lower trace shows a scaled version of the FM (Frequency Modulated) control input to the PLL, the uppermost trace containing transient spikes is the loop filter control voltage, and the smooth uppermost trace is the voltage on the main loop filter capacitor.

The cursor functions available within the simulation environment can be used to estimate the peak-to-peak output of the loop filter capacitor voltage and the time difference between the peak of the input signal and the peak of the loop filter response. The measured values can then be used to ascertain the peaking and phase delay of the output signal for the particular modulation frequency. The appropriate equations and methods are included in the associated lab session notes. A summary of the technique is also given in the section below on experimental hardware.

To provide a suitable transient response settling time the measurements should be taken after the PLL has settled, i.e. after about 3.5ms in the plot. Using the simulation model it is possible to alter the input modulation frequency and make further measurements to produce plots of the phase transfer function similar to the ones illustrated in Fig. 2.

Material relating to other measurements follows the same general format as that shown. Further supplementary information relating to the measurements is provided in the course lab notes.

Experimental hardware details and examples

The central part of the course material is the hardware demonstrator board. This board is based on a 74HCT7046(14) phase locked loop integrated circuit. This circuit element comprises the core of the demonstrator board and the internal operation is the same as that explained in the last section. An illustration of the demonstrator board outlining key components is provided in Fig. 6.