SiGe BiCMOS integrated circuits for high-speed serial communication links

Considerable progress has been made in integrating multi-Gb/s functions into silicon chips for data-and telecommunication applications. This paper reviews the key requirements for implementing such functions in monolithic form and describes their implementation in the IBM SiGe BiCMOS technology. Aspects focused on are the integration of 10-13-Gb/s serializer/deserializer chips with subpicosecond jitter performance, the realization of 40-56-Gb/s multiplexer/demultiplexer functions and clock-and-datarecovery/clock-multiplier units, and, finally, the implementation of some analog front-end building blocks such as limiting amplifiers and electro-absorption modulator drivers. Highlighted in this paper are the key challenges in mixed-signal and analog integrated circuit design at such ultrahigh data rates, and the solutions which leverage high-speed and microwave design and broadband SiGe technologies.

1. Introduction

The continuing demand for new communication services and higher user-end bandwidth has necessitated the development of Ethernet [1], Fibre Channel [2], and Synchronous Optical NETwork (SONET) [3] standards for transmission at data rates of > or =10 Gb/s, backed by the development of hardware capable of supporting such data rates. For example, the 10-Gb/s Ethernet standards activity which targets the broadband local area network (LAN) and wide area network (WAN) applications was completed before the end of 2002. For telecommunication applications, a well-established standard for 10-Gb/s serial links has also been defined by SONET OC-192 [3], which calls for a line rate of 9.95 Gb/s. Telecommunication equipment for higher-data-rate standards [such as SONET OC-768 [3] at 40 Gb/s and its variants with forward-error correction (FEC) at 43-50 Gb/s] for high-capacity long-haul applications is currently being commercialized.

As these very-high-data-rate communication markets continue to mature, they generate a pressing need for higher levels of integration to bring down the cost and power dissipation. However, this must be achieved while still complying with stringent serial link requirements such as minimizing jitter and bit-error rate (BER). In order to put some of these requirements into perspective, consider an example based on a realistic serial link jitter budget: A clock generator at the transmitter of a 10-Gb/s link must typically have less than 10% peak-to-peak jitter in order to enable a total link BER better than 10-12. Assuming that the equivalent noise source is white, one can show that this pcak-to-peak requirement translates to a sub-0.7-ps rms jitter generation specification, indicating a key challenge for circuit designers-how to design high-performance clocking circuits while keeping power dissipation low. In addition, one must still aim at high levels of integration, which may include all of the analog and digital functions related to serialization, deserialization, coding, framing, and built-in self-test (BIST). It is well known that whenever analog and digital circuits are used on the same chip, deleterious crosstalk and substrate coupling may occur, especially at these speeds. These considerations clearly show that circuit designers targeting such ultra-broadband applications will need all the help they can get from process technology developers. Among the more mature silicon-based technologies with high yields, the SiGe BiCMOS integrated circuit (IC) technology fulfills this need by providing high integration capability as well as high performance levels [4]. The remainder of this paper focuses on the IC design work done at the IBM Thomas J. Watson Research Center for 10-13-Gb/s and 40-50-Gb/s serial links using two generations of the IBM SiGe BiCMOS integrated circuit technology.

Compared to III-V integrated circuit technologies such as that based on the use of InP [5], the SiGe BiCMOS IC technology is viewed as a good candidate for implementing the relatively complex digital functions involved in clock and data recovery, serialization, and deserialization at data rates to 40 Gb/s and beyond. It is appropriate for these applications because it offers high-performance devices while enabling high levels of integration density. For ultrahigh-speed analog front-end circuits such as wideband and high-voltage amplifiers and electro-absorption modulator drivers, InP implementations have produced the strongest results in the industry to date. Even for these circuits, however, SiGe implementation performance, as described in this paper, is reaching a level at which key application requirements are clearly attainable. This is likely to drive a shift to SiGe for these designs, just as is currently occurring for the high-speed clock and data recovery, serialization, and deserialization functions in the 40-Gb/s arena.

The paper is organized as follows. A brief review of the IBM 0.5-[mu]m SiGe BiCMOS 5HP and 0.18-[mu]m SiGe BiCMOS 7HP integrated circuit technologies (hereafter designated simply as BiCMOS 5HP and BiCMOS 7HP, respectively) is given in section 2. BiCMOS 5HP is the most mature IBM SiGe generation and has been used extensively in our 10-13-Gb/s serializer/deserializer (SerDes) work, as described in section 3. The design and hardware characterization details of all of the SerDes building blocks, such as the voltage-controlled oscillators (VCOs), transmit and receive phase-locked loops (PLLs), and multiplexer/demultiplexer, as well as the fully integrated 10.3125- and 12.5-Gb/s versions of the SerDes chip, are discussed in that section. More demanding bandwidth and jitter requirements of OC-768 applications require the use of BiCMOS 7HP, as described in sections 4 and 5. SerDes building blocks operating at 40-56 Gb/s with half-rate 20-28-GHz clocks are reviewed in detail in section 4. Some of the challenges of packaging and testing at these speeds are also discussed. Section 5 contains an overview of two analog front-end functions and their implementation for SONET OC-768 in BiCMOS 7HP, namely the limiting amplifier and the electro-absorption modulator (EAM) driver. The hardware results from the EAM driver work show that SiGe heterojunction bipolar transistors (HBTs) can address high-voltage drive applications, in contrast to what is commonly assumed. The significance of accurate modeling of both active and passive devices including interconnection wiring is also highlighted in that section. Finally, a summary of the current status and potential directions for the future are presented in section 6.