Plasma-assisted chemical vapor deposition of dielectric thin films for ULSI semiconductor circuits

Plasma-assisted deposition of thin films is widely used in microelectronic circuit manufacturing. Materials deposited include conductors such as tungsten, copper, aluminum, transition-metal silicides, and refractory metals, semiconductors such as gallium arsenide, epitaxial and polycrystalline silicon, and dielectrics such as silicon oxide, silicon nitride, and silicon oxynitride. This paper reviews plasma-assisted chemical vapor deposition (CVD) applications and techniques for dielectric thin films. In particular, we focus on the integration, process, and reliability requirements for dielectric films used for isolation, passivation, barrier, and antireflectivecoating applications in ultralarge-scale integrated (ULSI) semiconductor circuits. In addition, manufacturing issues and considerations for further work are discussed.

Introduction

The fact that a gas discharge containing charged (ion) and neutral (radical) species can be used to initiate chemical processes has been known for over a century [1]. In later studies, other material-transport phenomena using a highfrequency discharge with an applied external electrode had also been observed [1]. With regard to the latter, the first experimental result, by Anderson in 1962, showed that a radio frequency (rf) voltage can be applied inside a glass tube to create reactive species for thin-film deposition [2]. The following year, Atl et al. showed that this plasmaassisted CVD (or simply "plasma CVD") process could be used for microelectronic applications, especially for diffusion masks and passivation [3, 4]. However, the use of plasma-assisted deposition processes for microelectronic circuit manufacturing was not seriously considered until the introduction of commercial batch processing equipment in 1974 [5, 6]. Since then, plasma-assisted deposition processing has moved from research and development lines into current product manufacturing lines for integrated circuits (ICs). More research, development, and manufacturing applications of thin films formed by plasma deposition have appeared in the technical literature and various commercial products, especially for microelectronic devices, as discussed in many recent publications [7-Il].

In recent years, new materials requirements and lowerprocessing-temperature requirements in ULSI circuits, solar energy cells, flat-panel displays, and optical systems have made plasma-assisted deposition processes increasingly important. In general, films of silicon-based semiconductors and insulators such as boron-doped or phosphorus-doped and intrinsic amorphous silicon, silicon oxide, phosphorus-doped and/or boron-doped silicon oxide, silicon nitride, and silicon oxynitride deposited by plasma-assisted CVD are most frequently used in solar energy cells [12], xerography [13], thin-film transistors for active-matrix liquid crystal displays [14-16], and ICs. There are many reviews of plasma deposition processes [17-19], relevant theory and reaction mechanisms [17, 20, 21], critical issues and parameters [22], and applications in IC fabrication [7-11, 22-24].

Current requirements for ULSI applications

Five principal types of silicon-based thermal and plasma CVD dielectrics are currently used in IC fabrication: silicon oxide, silicon nitride, silicon oxynitride, phosphorus-doped silicon oxide (PSG), and boron/ phosphorus-doped silicon oxide (BPSG). Their properties can be modified to achieve desirable functions. For example, silicon-rich silicon oxide or nitride films can be used as charge-storage materials for erasable programmable read-only memory (EPROM) devices. The composition of silicon oxynitride can be tailored to meet specific photolithography and etching (or simply "etch") requirements as an antireflective coating (ARC) [25] and also to meet device and integration requirements as a barrier film for gate conductors (to be described later). The gap-filling (or simply "gap-fill") capability and degree of local planarization for high-density plasma (HDP) CVD oxide [26] can be adjusted by changing the deposition-tosputter-etching ratio (or simply "sputter-etch ratio") DIS, defined as (net deposition rate + blanket sputtering rate)/(blanket sputtering rate). The requirements change for HDP CVD oxide when considering it for use in shallow-trench isolation (STI) compared to use as an intermetal dielectric (IMD). For example, maintaining a wafer temperature less than 400C is critical for the IMD application for better metal reliability [27]. A higher temperature is desirable for the STI application, since a more dense film that is highly resistant to subsequent wet-etching steps is thus obtained. These applications are discussed in more detail later in the paper.

One of the major requirements and technology drivers for ULSI isolation and passivation dielectrics is the filling of sub-half-micron-wide gaps without voids. The film profile changes with the type of deposition process used. For conventional plasma-enhanced (PE) CVD processing, the deposited dielectric film takes on a "bread-loaf" profile, as illustrated in Figure 1. This type of profile is most pronounced with silane-based PECVD films. When tetraethylorthosilicate (TEOS) is used as the silicon source for PECVD oxide deposition, there is less cusping because of the higher surface mobility of the reactants [28]; however, a void still forms if the gap is small enough, because the conformality of the film is not 100%. This means that the amount of deposition on the sidewalls and bottom of the trench portion of a feature is less than on the top of the feature. So, in order to use PECVD films alone for gap-fill applications, they are typically used in conjunction with an argon sputter etch in a multistep PECVD-argon sputter etch-PECVD sequence described previously [29]. Conformal deposition is more typical for thermal (non-plasma) CVD processes such as low-pressure (LP) CVD at high temperatures or for ozone-TEOS atmospheric or subatmospheric pressure (AP or SA) CVD at lower temperatures (less than 600C). Furthermore, HDP CVD results in a completely different type of profile, as indicated in Figure 1, because of the "bottomup" deposition from the simultaneous deposition and etching. The resultant topography from any of these CVD processes plays a decisive role in the choice of subsequent planarization techniques.