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Cadence Extends the Analog Design Environment for Complex Mixed-signal Design Verification; Accurate Simulations up to 1,000 Times Faster than SPICE - Cadence Design Systems ATS 3.0 - Product Announcement

Edge: Work-Group Computing Report, May 8, 2000

Cadence Design Systems, Inc. (NYSE:CDN), the world's leading supplier of electronic design products and services, Monday announced a new version of its accelerated transistor-level simulator (ATS).

ATS3.0 allows Cadence analog design environment users access to high-performance simulation and verification of mixed-signal designs. A direct integration of ATS into the Cadence analog design environment allows for ease of use, capacity, and simulation performance of mixed-signal designs not previously available. The advanced features of ATS permit it to quickly and accurately verify much larger designs than is currently possible with traditional simulation techniques, thus bridging the simulation gap for combining complex analog, digital transistor, gate level and hardware description language (HDL) design verification. In addition, the latest release features support for measurements, enhanced partitioning algorithms and faster simulation on a number of circuit topologies.

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Tying ATS to the Cadence analog design environment -- the world-standard for analog designers with an installed base of more than 15,000 users -- provides a solid platform for a variety of essential functions. Cadence's analog design environment is the only complete front-to-back analog design platform for full-custom and semi-custom analog, mixed-signal, and radio frequency integrated circuit design (RF IC). The environment integrates a wide range of powerful and proven tools designed to meet the specific needs of designers in various industries such as telecommunications, computer, multimedia, automotive, and aerospace.

ATS For High-Speed Simulation

ATS is an accelerated, transistor-level, time-domain simulator specifically developed for very large, custom digital and mixed-signal circuits. It combines the high speed of metal oxide silicon (MOS) timing simulation with the accuracy of traditional analog simulation provided by simulation program with integrated circuit emphasis (SPICE) simulators. This gives mixed-signal designers a faster simulation method by using a higher speed engine (MOS timing) that is 100 to 1000 times faster than SPICE with high levels of accuracy (within 5 percent of SPICE).

Other commercially available MOS timing simulators have problems handling precision analog and bipolar circuits accurately. ATS, however, partitions analog designs and applies the appropriate analyses automatically. This partitioning with multi-rate simulation speeds up analog circuit simulation since smaller partitions use smaller matrices with quicker convergence and each partition can have its own time step. ATS is integrated with Cadence Verilog and very high-speed integrated circuit hardware description language (VHDL) simulators, extending its application into the digital HDL domain.

"Combining mixed MOS timing and SPICE algorithms makes it possible to simulate many large transistor-level circuits that are untouchable today," said Mark Williams, product manager, Custom IC solutions marketing. "Rather than hitting the wall at 10,000 transistors with SPICE, designers can get SPICE-like accuracy, at a higher speed, and in a familiar, trusted design environment with ATS."

Pricing and Availability

ATS integrated with Cadence analog design environment is available in limited quantities now, with volume shipments commencing June 2000. For the Cadence ATS simulator, one-year U.S. list price is $39,600 and it is available on UNIX-based workstations from Sun Microsystems and Hewlett-Packard. Additional information on the product and international pricing is available from local Cadence sales offices.

Cadence is the largest supplier of software products, methodology services, and design services used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,000 employees and 1999 annual revenue of $1.1 billion, Cadence has sales offices, design centers, and research facilities around the world. The Company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services may be obtained from the World Wide Web at http://www.cadence.com.

Technology Industry

Cadence Extends the Analog Design Environment for Complex Mixed-signal Design Verification; Accurate Simulations up to 1,000 Times Faster than SPICE - Cadence Design Systems ATS 3.0 - Product Announcement

Edge: Work-Group Computing Report, May 8, 2000

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