Accuracy in interleaved ADC systems - analog-to-digital conversion in the HP 54720 series oscilloscopes and HP 54722A and HP 54721A plug-in modules - includes related articles on bit limits on resolution and dithering, and on designing filters for interpolation - Technical

Hewlett-Packard Journal,  Oct, 1993  by Allen Montijo,  Kenneth Rush

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The overall performance of the HP 54720 oscilloscope is the result of the synergistic effects of calibration, signal preconditioning, and data postprocessing.

Why would someone choose to implement a time-interleaved ADC system instead of simply using the latest technology to implement a single ADC with the desired performance? Simply put, a time-interleaved ADC system can achieve superior performance, given the same implementation technology. For a given technology, there is theoretically no limit to the sample rate that can be reached using interleaving methods, although there is a limit to the bandwidth and thus the usefulness of interleaving. Real-world limitations such as power and space place practical limits on the level of interleaving that can be achieved. For the HP 54720 oscilloscope, these limits allowed us to put four 500-MSa/s ADCs onto a single hybrid to achieve a maximum sample rate of 2 GSa/s. With the HP 54722A plug-in, all four hybrids are interleaved to achieve sample rates up to 8 GSa/s in one instrument. Sixteen ADCs on four hybrids work together to sample at consistent intervals of 125 ps with a signal bandwidth of nearly 2 GHz.

Interleaving is accomplished by routing the input signal to all ADCs and providing a conversion clock with a suitable phase to each ADC (see article, page 11). One ADC hybrid in this instrument contains four ADCs, each capable of sampling at 500 MSa/s. The input is split four ways, sampled, and fed to the four ADCs. Each of these four signal paths is furnished a clock, which is used to coordinate sampling and digitization. In this system all four clocks run at 500 MHz at all sample rates, giving an overall data rate of 2 GSa/s per hybrid. Circuitry on the sampler IC controls the phasing of the clocks while circuitry on the ADC ICs decimate the data to the correct rate (see Fig. 1).

To illustrate some of the problems that interleaving creates, look at a simple system that interleaves two 1-GSa/s ADCs to achieve 2 GSa/s. For ease in understanding, assume that the ADCs have infinite resolution. The results obtained apply to real ADCs with finite resolution on a statistical basis.

An offset difference between the two ADCs is digitized to different codes by the ADCs. Since the ADCs output data alternately, the output data values exhibit a pattern with a period equal to the sample rate of an individual ADC, or 1 GHz in this example (Fig. 2). The error signal is not a function of the input signal, but only of the difference in offset. When N ADCs are interleaved, the basic period of the error signal remains the same (the sample period of a single ADC), but the frequency content can increase because each cycle of the error signal contains N values and N arbitrary offset errors.

Fig. 3 demonstrates that if there is a difference in voltage gain between the two ADCs, mixing occurs. If a sine wave is applied to the system, the largest difference in ADC outputs occurs at the peaks of the sine wave. As with an offset error, the basic error occurs with a period equal to the sample rate of an individual ADC, but the magnitude of the error is modulated by the input frequency. In this example, if a 20-MHz signal is applied and the two ADCs have a difference in gain of 10%, then the envelope of the error signal is 5% as large as the 20-MHz input. The error signal is a 1-GHz carrier that is amplitude modulated by the 20-MHz input signal. With a full-scale sine wave input and a 0.25-dB mismatch in gain (<3%), the effective bits parameter is limited to 5.8 by this source of error alone. Increasing the number of ADCs that are interleaved increases the number of frequencies that are available as carriers. All harmonics of the individual ADC sample rate can simultaneously be carriers.

An error in timing shows a similar result (Fig. 4). The samples are supposed to be precisely 500 ps apart. If they are 510 ps and 490 ps apart, then there is a 20-ps skew between the ADCs. This timing skew will show the largest error where the signal has the highest slew rate, or at the zero crossings. The envelope of the error signal will be largest at the zero crossings and will have a period equal to the period of the input signal. Once again, the basic error signal has a period equal to the sample rate of an individual ADC. The error from a timing skew is identical to the error from a gain difference, except that its envelope is shifted by 90 degrees and its magnitude is frequency dependent. In this case the 1-GHz carrier is amplitude modulated by the derivative of the input signal. With a 1-GHz input signal and a time skew of 4 ps, the number of effective bits is limited to 6.0 by this source of error alone.

The three sources of error just described are straightforward to deal with. Unfortunately, other errors are not so simple. Differences in frequency response between the signal paths create gain and phase (timing) errors that are a function of frequency. These differences can be caused by process variations, which affect the positions of poles and zeros in the response, and by nonsymmetric coupling between the signal paths.