MOSFET scaling into the future

Hewlett-Packard Journal,  August, 1997  by Paul Vande Voorde

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One obvious solution to control quiescent power consumption is to put almost all the circuit in power-down mode at any instant and activate only those blocks that are being accessed. This system-level type of solution is beyond the scope of this paper and needs to be evaluated by the design community.

Another possible solution that has been proposed involves multiple threshold devices in the same technology. For example, the 0.1-[Mu]m generation could offer FETs with [V.sub.t] = 0.2V and [V.sub.t] = 0.4V. The low-[V.sub.t] FETs could be used for speed-critical paths and the higher-[V.sub.t] FETs could be used for tasks for which speed is not as important.

After modifying the doping profiles in TSUPREM-4 to get higher thresholds, the MEDICI simulations were repeated and new SPICE models extracted. Fig. 12 shows the resulting drive current and off-state current for various values of [V.sub.t] in the 0.1-[Mu]m generation. Fig. 13 shows the gate delay as a function of [V.sub.t]. From these graphs, FETs with [V.sub.t] = 0.4V would yield gate delays about 80% longer than [V.sub.t] = 0.2V but with off-state currents reduced by nearly three orders of magnitude. Again, the off-state currents shown are for nominal devices and worst-case would be higher. This approach is conceptually easy to implement in any technology. However, it increases the complexity of both the process and the circuit design.

Fully depleted (FD) silicon-on-insulator (SOI) devices have been proposed to reduce off-state current for a given [V.sub.t]. These devices have a steeper subthreshold slope than conventional bulk devices, thus reducing off-state current without increasing [V.sub.t]. However, single-gate FD SOI devices are difficult to scale into the deep submicrometer regime. Dual-gate FD SOI devices scale much better but are very complicated to make. These difficulties, coupled with the material quality and availability issues, make the FD SOI device an unlikely candidate for future generations of high-speed digital technology.

If no other solution for high [I.sub.off] can be found, then [V.sub.t] cannot be scaled lower than a certain point. For example, if one needed to keep [I.sub.off] (nominal) at 1 nA/[Mu]m, then [V.sub.t] (nominal) could not go below about 0.35V. We can apply this to the 0.1-[Mu]m generation [T.sub.ox] = 2.5 nm) and resimulate the device with [V.sub.t] = 0.35V. After compact model extraction and inverter simulations, we find that [V.sub.dd] must be increased to 1.8V to get the same performance as shown in Fig. 10 for the 0.1-[Mu]m generation. At [V.sub.dd] = 1.8V and [V.sub.t] = 0.35V, the device simulations predict a drive current of slightly over 1 mA/[Mu]m (NMOS). The peak oxide field would be over 7 MV/cm and the peak electron temperature would be about 3300K at [V.sub.d] = [V.sub.g] = 1.8V (compare to Fig. 7). Even if we could obtain this very high drive current, it is questionable whether such a device could be created with adequate reliability. In any case, it is clear from this discussion that ceasing threshold voltage scaling would have a crucial impact on future device technologies.