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MOSFET scaling into the future

Hewlett-Packard Journal, August, 1997 by Paul Vande Voorde

2D process and device simulators have been used to predict the performance of scaled MOSFETs spanning the 0.35-[Mu]m to 0.07-[Mu]m generations. Requirements for junction depth and channel doping are discussed. Constant-field scaling is assumed. MOSFET drive current remains nearly constant from one generation to the next and most of the performance improvement comes form the decreasing supply voltage. Gate delay decreases by 30% per generation, nearly the same trend as previous generations. However, this performance gain comes at the price of much higher off-state leakage because of the reduction of the threshold voltage. Various solutions to this high leakage are discusses.

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Hewlett Packard adopted CMOs technology in the mid-1970s. At that time the gate length [L.sub.g] was 4 [Mu]m and the gate oxide thickness [T.sub.ox] was 50 nm. Since then, each new generation of technology has shrunk [L.sub.g] by about 30% and [T.sub.ox] by about 25%. The decrease in [L.sub.g] has been tied to the evolution of lithography equipment. Following these scaling trends, intrinsic gate delay has decreased about 30% per generation. New generations of technology are released about every three years. The important principle in MOSFET scaling is that [L.sub.g] and [T.sub.ox] must decrease together. Scaling one without the other does not yield adequate performance improvement.

The performance metric for gate delay is CV/I, where C is the load capacitance, V is the supply voltage ([V.sub.dd]), and I is the drive current of the MOSFETs (average of NMOS and PMOS). C is composed of both gate and junction capacitance. MOSFET scaling, which decreases [L.sub.g], [T.sub.ox], and junction area while increasing substrate doping, tends to keep C fairly constant from generation to generation. For several generations of technology, the supply voltage was held constant at 5V (constant-voltage scaling). In that era, gate delay was reduced by ever-increasing MOSFET drive currents. Since the voltage was held constant while the dimensions decreased, the electric fields continuously increased. High fields and high currents tend to damage the gate oxide and lead to device deterioration. Thus, one of the main technology challenges has been to design MOSFETs with adequate reliability.

Constant-voltage scaling ended as [L.sub.g] approached 0.5 [Mu]m and [T.sub.ox] neared 10 nm. The demands of gate oxide reliability required that the supply voltage be reduced. This occurred as the peak oxide field reached roughly 4 MV/cm. We are now in an era where supply voltage is scaled along with [T.sub.ox] so that the peak oxide electric field remains roughly constant (constant-field scaling). This study examines some of the implications for this of type scaling in future technology generations.

Process and Device Simulations

The 2D process simulator TSUPREM-4 from Technology Modeling Associates Inc. of Sunnyvale, California was used to simulate scaled MOSFET device structures. The inputs to TSUPREM-4 are the implant and oxidation steps that would be used in the actual process. The process architecture assumed is similar to current CMOS processes, employing shallow source/drain extensions and deeper main source/ drain regions followed by silicidation.

The 2D device simulator MEDICI, also from Technology Modeling Associates Inc., was used to predict the electrical characteristics of the device structures from TSUPREM-4. Here we use field dependent mobility models that have been benchmarked to the HP CMOS10 process. Iterative simulations with TSUPREM-4 and MEDICI were performed to determine the requirements on junction depth and channel doping profile to ensure proper threshold and subthreshold behavior. Fig. 1 shows the device structures resulting from these simulations for each generation from 0.35 [Mu]m down to 0.07 [Mu]m. For [L.sub.g] less than 0.15 [Mu]m, retrograde channel doping profiles are needed to control the subthreshold characteristics.

Figs. 2 through 5 summarize the results of this scaling study. Fig. 2 shows the scaling of [T.sub.ox] with [L.sub.g]. These two must scale together to get adequate performance improvement. Constant field scaling dictates that [V.sub.dd] must decrease proportionally to [T.sub.ox], maintaining a peak oxide field of 4 MV/cm. For example, this results in [T.sub.ox] = 2.5 nm and [V.sub.dd] = 1V for the [L.sub.g] = 0.1 [Mu]m generation.

Fig. 3 shows the scaling of effective channel length (L.sub.eff]) and the source/drain extension junction depth ([X.sub.j]). For the 0.1-[Mu]m generation, [L.sub.eff] is about 0.07 [Mu]m and [X.sub.j] must be nearly 50 nm. The series resistance of the source/drain extension must decrease even as the junction depth also decreases. This requires higher doping levels in the extension region and carefully minimized spacer widths.

Fig. 4 shows the scaling of threshold voltage ([V.sub.t]). Here [V.sub.t] is kept at 20% of [V.sub.dd] to maintain adequate current drive. This yields [V.sub.t] = 0.2V for the 0.1-[Mu]m generation. Unfortunately, since off-state current varies exponentially with [V.sub.t], reducing [V.sub.t] leads to much higher off-state leakage current (100 nA/[Mu]m for the 0.1-[Mu]m generation) than in current CMOS technologies. Here the simulations are tailored to predict the nominal leakage. Worst-case leakage would be approximately one order of magnitude higher for the 0.1-[Mu]m case.

Technology Industry

MOSFET scaling into the future

Hewlett-Packard Journal, August, 1997 by Paul Vande Voorde

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