Analog behavioral modeling and mixed-mode simulation with SABER and Verilog

Hewlett-Packard Journal,  April, 1997  by Ben B. Sheng,  Hugh S.C. Wallace,  James S. Ignowski

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In parallel with the system simulations, high-level simulations using SABER and Verilog were being run with analog block models. The high-level simulations performed functional and timing checks of the digital control blocks and their interfaces to the behavioral representations of the analog blocks. In this way, the operation of analog circuitry under the control of complex state machines was verified. The results of high-level simulations of the analog portion of the system were compared to the results of the Mathematica system model for verification. Analysis and debugging of the analog behavioral simulation results were valuable for modeling and for confirming observations from the test and characterization of first silicon.

Critical Analysis

The read/write channel chip was our first major chip design for which high-level system design and verification were extremely critical to the chip's performance. Many previous mixed-signal designs depended on just the individual functional blocks' meeting the specifications to ensure that the final chip would perform to the system specifications. For the read/write channel chip, the system performance and trade-offs could only be evaluated after much of the actual circuit design was completed. The system performance of the read/write channel chip was extremely sensitive to a number of nonidealities in the signal path, so multiple iterations were carried out between careful circuit characterizations and system performance evaluations.

After the project was finished, and with an increasing need to define formally a methodology for new mixed-mode signal processing chips, the strengths and weaknesses of the read/write channel chip methodology were evaluated.

The high-level SABER models verified that the digital control circuitry functioned correctly with the analog blocks. This contribution cannot be overstated. The number of signals together with the complex interaction between the digital and analog blocks cannot be checked adequately in any other manner. The behavioral modeling of the analog blocks also discovered problems within the analog circuitry. While many of the main related analog blocks were simulated in SPICE together, there were others that were not, because of size and speed limitations in SPICE. The netlist extraction for the top-level SABER simulations was automatically generated from the chip transistor schematic, so the high-level simulations gave good confidence that the chip was correctly connected.

The main weakness in the process was that one engineer was responsible for developing all the analog behavioral models. This was because of manpower constraints in this project and the new introduction of the SABER tools. The investment in the learning curve for the new tools could not be absorbed by this project. The process that was followed to develop more than 100 behavioral models was examination of the schematics and SPICE plots that were available, and communication with the block designers. This worked fairly well in most cases, but there were some instances of incorrect behavioral modeling. The main problem was that human interpretation was needed to create the behavioral models. Characterization tests to compare the circuits with the models could have helped, but with so many blocks, some being continuously modified, a full set of characterization tests was not practical with the given amount of time and resources.