Analog behavioral modeling and mixed-mode simulation with SABER and Verilog

Hewlett-Packard Journal,  April, 1997  by Ben B. Sheng,  Hugh S.C. Wallace,  James S. Ignowski

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The ADC model not only evaluates signals in the analog domain, but also schedules digital events. As mentioned earlier, the newer-generation simulators not only provide SPICE-like analog simulation engines, but also have built-in digital simulators, which give them much improved performance in simulating mixed-mode systems. Built-in digital simulators are orders of magnitude faster in simulating digital circuits than a SPICE-like simulator. We will discuss mixed-mode simulations in more detail later.

Medium-Level Modeling

Medium-level modeling refers to behavioral modeling of smaller building blocks, such as an operational amplifier (op amp), a multiplier, an integrator, or a comparator. These circuits typically contain a few dozen transistors. Models for these circuits can have more physical characteristics, which track SPICE simulation results.

For modeling the read/write channel chip, we used medium-level models most extensively. Three different techniques were used to develop the models, based on the different circuit structures.

The first approach is to create generic building blocks with flexible parameters that can be used to customize these generic models when they are used in different applications. A good example for this approach is the model for an op amp. Characteristics of a generic op amp include dc gain, pole location (if a second pole location is important, one can simply connect two one-pole models in series), zero location, input impedance, input capacitive load, output impedance, output capacitance, output common-mode level, slew rate, output swing, and nonlinear distortion. More comprehensive characteristics can be added to this list when needed. Fig. 2 shows an example of such a generic op amp model. Some of the parameters listed above are omitted for brevity.

Fig. 2. An example of a generic op amp model.

1 template opamp inp inm outp outm vcm vdd gnd pd = ci, gm, gm3, vswing, ro,

co, rz, imax

{

c.cip inp 0 = ci

c.cim inm 0 = ci 5 values {

# Define the block's inputs

vint = v(inp, inm)

vinp = v(inp)

vinm = v(inm) 10 if (v(inm) > v(inp)) {

vinp = v(inm)

vinm = v(inp)

}

# Gain and 3rd order nonlinear distortion 15 idiff = gm*vint + gm3*vint**3

# Output swing, the output clips at "vswing"

iclip_up = (vswing - v(outp, outm))/ro/1k

iclip_dn = (vswing - v(outm, outp))/ro/1k

if (v(outp, outm) > vswing) { 20 iclip_up = iclip_up*10meg

}

else if (v(outp, outm) < -vswing) {

iclip_dn = iclip_dn*10meg

} 25 idiff = idiff + iclip_up - iclip_dn;

# Slew rate

if (idiff > imax) idiff = imax

if (pd ~= 14_0) idiff = 0

} 30 equations

# A pole and a zero

icapp = d_by_dt ((v(outp) - icapp*rz)*co)

icapm = d_by_dt ((v(outm) - icapm*rz)*co)

i(outp) -= ioutp 35 ioutp: ioutp = idiff - v(outp, vcm)/ro - icapp

i(outm) -= ioutm

ioutm: ioutm = -idiff - v (outm, vcm)/ro - icapm

}