Analog behavioral modeling and mixed-mode simulation with SABER and Verilog

Hewlett-Packard Journal,  April, 1997  by Ben B. Sheng,  Hugh S.C. Wallace,  James S. Ignowski

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# Looking for rising edges in clk.

if (clk == 14_1 & clk_last == 14_0) { 10 schedule_event (time, b2, 14_x)

schedule_event (time, b1, 14_x)

schedule_event (time, b0, 14_x)

# Tell the analog simulator to step on the clock edge to get accurate

# analog signal value 15 schedule_next_time (time)

# Sample input voltage (with some adjustment for correct zeroing)

# and reference voltage

vref = v(ref)

vin = v(in) + vref/8 20 # Error checking

if (vref < 0) error ("The voltage reference to the ADC is negative")

if (abs(vin) > vmax) error ("The ADC input signal is out of range")

# Determine the sign bit

if (vin < 0) d2 = 0 25 else d2 = 1

# Add random differential nonlinearity

vin = abs (vin) + (2*rand() -1) *dnl

# Clipping the output

if (vin > vref) vin = vref 30 # Add random integral nonlinearity

vin = vin + random_inl* (vref - abs(vin))*abs (vin) *4/vref/vref

if (vin < vref/2) d1 = 0

else {

d1 = 1 35 vin = vin - vref/2

}

if (vin < vref/4) do = 0

else {

d0 = 1 40 vin = vin - vref/4

}

# Compute resolution time. If td+t_resolve > 1-clock-cycle, then the

# ADC is in a metastable state (a conversion error occurs)

t_resolve = tau*ln (2/ (abs (vin) +1u)) 45 if (d2 == 1) schedule_event (time+td+t_resolve, b2, 14_1)

else schedule_event (time+td+t_resolve, b2, 14_0)

if (d1 == 1) schedule_event (time+td+t_resolve, b1, 14_1)

else schedule_event (time+td+t_resolve, b1, 14_0)

if (d0 == 1) schedule_event (time+td+t_resolve, b0, 14_1) 50 else schedule_event (time+td+t_resolve, b0, 14_0)

}

}

}

As can be seen in this example, high-level modeling can be used in describing analog and mixed-mode subsystems, with some detail included. This particular approach is suitable for functional simulations of large systems. A large number of functional simulations can be carried out quickly, but circuit details are often omitted. This type of high-level modeling can speed up simulations by at least three orders of magnitude compared to SPICE, at the cost of not being able to simulate the fine details in the circuits.

For complex mixed-signal designs chip-level connectivity verification is often a problem, since neither traditional analog simulators such as SPICE nor pure digital simulators such as Verilog can, for example, check voltage reference levels or common-mode levels of differential signals. One of the most important benefits of using high-level models is the ability to verify top-level circuit connectivity when the final chip is composed. One specific example is given in the ADC model of Fig. 1. Line 21 checks that the reference voltage to the ADC is not connected incorrectly (negative reference).

Another key point is the ability to do analog assertion. Traditional graphical analog postprocessors work well if there are a manageable number of signals and time windows to look at--in other words, when dealing with simulation results of a relatively small circuit. For system-level simulations, in which multiple complex analog blocks interact with each other and hundreds of signals are changing constantly, it becomes very difficult to track all the important signals to make sure that all the circuits are operating within their specified parameters. The analog modeling language allows designers to put specific assertions in the models to monitor the analog signals and give warning messages or even abort simulations when the model is operating outside of a set of prespecified parameters. An example of such an assertion can be seen in line 22 of Fig. 1, where the input signal is compared to a prespecified maximum level.