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Analog behavioral modeling and mixed-mode simulation with SABER and Verilog

Hewlett-Packard Journal, April, 1997 by Ben B. Sheng, Hugh S.C. Wallace, James S. Ignowski

A description is given of specific analog behavioral modeling and mixed-mode simulation techniques using SABER and Verilog. Full-channel simulations have been carried out on a class I partial response maximum likelihood (PRML) read/write channel chip. Complex analog circuits such as an adaptive feed-forward equalizer, an automatic gain control block, and a phase-locked loop are modeled in detail with the SABER MAST mixed-signal behavioral modeling language. A simulation speedup of two orders of magnitude has been achieved compared to SPICE.

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For more than two decades, the analog IC design community has been relying on variations of the original Berkeley SPICE, introduced in the 1970s, as the simulation tool for verifying and fine-tuning analog designs. Over the years, many enhancements have been put into these different flavors of SPICE, while increasingly more powerful computers have been used for running these circuit simulations. However, SPICE remains a low-level circuit simulator. It produces accurate results, but is inherently slow. Today's analog and mixed-mode designs are becoming increasingly complex. Functional simulations for larger mixed-signal designs are impractical with SPICE. Meanwhile, as the pressure increases for low-cost, high-integration ASICs ("systems on a chip"), many analog functions are being integrated into largely digital chips. The need for new simulation methodologies is becoming more urgent.

In recent years, benefits from using analog and mixed-mode behavioral modeling languages have received increased recognition. The basic approach is to use a SPICE-like continuous-time simulator, which provides good accuracy in simulations, together with a fast digital simulator to give orders of magnitude faster digital circuit simulations. The modeling language is flexible so that designers can model analog subsystems in different levels of abstraction. The modeling language gives designers control over the trade-off between simulation speed and accuracy.

This paper presents some of the bottom-up modeling techniques and simulation approaches that have been adopted during the process of modeling and simulating the read-write channel chip for an HP DDS-3 DAT drive.

Analog Behavioral Modeling

The idea of behavioral modeling is not new to analog designers. Macro models have been widely used by SPICE users. The newer-generation mixed-mode circuit simulators, such as SABER by Analogy, Inc. and SPECTRE by Cadence Design Systems, Inc., have greatly enhanced designers' ability to model analog and mixed-mode circuits and systems by providing a flexible behavioral modeling language. With this modeling language, a designer can behaviorally describe an analog or mixed-mode device or subsystem at whatever level of abstraction is appropriate for a given simulation accuracy-versus-speed trade-off One can use this modeling language to write BSIM models for MOS transistors and use these BSIM models to achieve simulation results that are as accurate as those from SPICE simulations. The same modeling language can be used to describe an analog-to-digital converter (ADC) behaviorally, without having to refer to any of its internal circuit elements.

Several modeling approaches are discussed in this section. Based on the scopes of these different approaches and their simulation speed-versus-accuracy trade-offs, they can be categorized as either high-level, medium-level, or low-level modeling. In the following subsections, specific examples are given for high-level and medium-level modeling. Although low-level modeling is a very important part of analog modeling and simulation, the techniques used to do low-level modeling are very similar to those used in higher-level modeling. The only difference is that these techniques are used to model much smaller devices, such as MOSFETs, diodes, and bipolar junction transistors. For brevity, discussion of low-level modeling is omitted.

High-Level Modeling

High-level modeling refers to behavioral models that describe large analog and mixed-mode subsystems in a high level of abstraction. This approach provides the fastest simulation speed but the least detail in the circuits that are modeled.

An ADC can be modeled with a clock input signal that triggers each conversion, an analog input signal, an analog reference signal, and digital outputs. In addition to this basic structure, some realistic behavior can be included in the model. For example, the model can include characteristics such as differential nonlinearity, integral nonlinearity, and metastability characteristics. A behavioral 3-bit ADC model written in the SABER MAST modeling language is shown in Fig. 1.

Fig. 1. A behavioral 3-bit ADC model written in the SABER MAST modeling language.

1 template adc clk in ref b2 b1 b0 = tau, td, dnl, inl, vmax

{

# Capacitive input load of 1 pF

c. input_load in 0 = 1p 5 # Compute a random integral nonlinearity

number random_inl = (2*rand() -1)*inl

when (event_on (clk, clk_last)) {

Technology Industry

Analog behavioral modeling and mixed-mode simulation with SABER and Verilog

Hewlett-Packard Journal, April, 1997 by Ben B. Sheng, Hugh S.C. Wallace, James S. Ignowski

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