Designing, simulating, and testing an analog phase-locked loop in a digital environment

Hewlett-Packard Journal,  April, 1997  by Thomas J. Thatcher,  Michael M. Oshima,  Cindy Botelho

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In designing a phase-locked loop for use on several HP ASICs the digital portion of an existing phase-locked loop was transferred to a behavioral VHDL description and synthesized. A behavioral model was written for the analog section to allow the ASIC designers to run system simulations. A new leakage test was developed that has been very effective in screening out process defects in the filter of the original design.

This paper describes the design and integration process for a phase-locked loop that is being used on several current HP ASICs (application-specific integrated circuits). The design is based on the phase-locked loop for a previous ASIC, but several improvements were made. First, the digital portion of the phase-locked loop was transferred to a behavioral VHDL(*) description and synthesized. Reusability was a big consideration in writing the code. The portable nature of the VHDL code enabled us to design several phase-locked loops within a very short time. Second, a behavioral model was written for the analog section to allow the ASIC designers to run system simulations. This model, when combined with the model for the digital section, allows the designer to simulate the phase-locked loop as it locks--it does not merely put out an ideal clock waveform. Finally, in a previous ASIC, a large resistor and capacitor in the loop filter were not adequately tested. For the new phase-locked loop, we developed a leakage test that has been very effective in screening out process defects in the filter.

An analog phase-locked loop presents several challenges to designers in an all-digital design environment. Some all-digital simulators, such as Verilog XL, cannot represent analog signals easily. System designers must either use a mixed-mode simulator to represent the analog portions of the phase-locked loop, or use a simplified model of the phase-locked loop. In ASIC production test, limitations of the production test equipment must be taken into account. For example, an analog measurement may take a long time to complete. Also, functional testers cannot measure frequency, so it is difficult to determine that the phase-locked loop is operating properly in production test.

Previous Phase-Locked Loop Design

The previous phase-locked loop design appeared on an ASIC, where its purpose was to accept an input clock (the video clock) and generate the system clock. The clock signal output from the phase-locked loop was modulated so that the output clock frequency alternated back and forth between two frequencies slightly above and below the target system clock frequency. This frequency modulation of the system clock was required by the system in which the previous design was used.

The block diagram of the previous phase-locked loop is shown in Fig. 1. The loop consists of an input counter (divide-by-M), a feedback counter (divide-by-N), a phase-frequency detector, a charge pump and filter, a voltage-controlled oscillator (VCO), and other digital control logic. The input counter divides the input clock by either [N.sub.high] or [N.sub.low]. It produces an output pulse (FREF) that is low for one clock cycle and high for the remaining time. The feedback counter divides the VCO output by [N.sub.high] or [N.sub.low] It produces an output pulse (FBAK) that is low for two clock cycles. The phase-frequency detector examines the relative phase of the rising edges of the FREF and FBAK signals and generates pulses on the UP and DOWN signal lines. The charge pump uses these pulses to adjust the control voltage for the VCO. The output signal is generated by dividing the VCO output clock by 4. The resulting phase-locked loop output frequency is given by:

[Figure 1 ILLUSTRATION OMITTED]

(1) [f.sub.out] = 1/4 (N/M) [f.sub.i]

The control block consists of logic that selects one of the operating frequencies. A state machine in this block controls the modulation between the upper and lower frequencies. In normal mode, the control logic sets the phase-locked loop to the upper frequency when it is reset. The loop remains at the upper frequency until the control block receives a signal that indicates that the loop is locked. After this, the loop alternates between the upper and lower frequencies. This is controlled by the N_SEL and M_SEL outputs of the modulator counter.

There were two main problems with the integration of the phase-locked loop. The first problem was that there was no model of the phase-locked loop in VHDL or Verilog that could be used for system simulation. Therefore, no simulations were run with the clock generated by the phase-locked loop. All simulations were run with an external clock, using a different chip mode. This caused the design team to miss a serious bug in the design. When the mode pins were set to enable the phase-locked loop, one block inside the chip was accidently set into scan mode. This problem was not caught until the first prototype parts were placed on a board.

The second problem encountered with this phase-locked loop design was a high production line failure rate. The phase-locked loop tests were not catching all the defective parts. Analysis of the returned parts showed that the failures were caused by defects in the resistor and capacitor in the loop filter, which caused excessive leakage, changing the filter characteristics. The production tester had no way to test for this, so a new test had to be created. Here the lack of a good simulation model for the phase-locked loop was a real handicap. The original tests for the phase-locked loop were debugged on the tester. When trying out new tests, we had no way of simulating them to verify their correctness. Thus, it took two or three iterations before the tests were correct.