Viewlogic unveils ASIC move; Motorola tie

Electronic News,  June 10, 1996  by Judy Erkanat

Tags: ASIC, Motorola Inc., software

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Fremont, Calif.--Viewlogic Systems chose the Design Automation Conference in Las Vegas last week to announce the first step in its new ASIC 2000 project. To help eliminate bottlenecks in complex ASIC design, the company integrated Viewlogic technologies with strategic third-party tools to come up with the Datapath Design Solution, a verification methodology, and the Design-to-Test Solution.

At the same time, Motorola's Semiconductor Products Sector and Viewlogic's High Level Design Group announced an alliance to develop a next-generation ASIC design methodology to unify logical and physical design based on Viewlogic's PathBlazer datapath design tool, scheduled to be available from Viewlogic and supported in Motorola's design flows 3Q96.

Integrating, adding to and leveraging high-end point tools Viewlogic obtained through recent acquisitions, the new products take on competitors Synopsys, Mentor Graphics and Cadence Design Systems.

The Datapath Design Solution centers on the PathBlazer datapath synthesis tool, allowing designers to explore and optimize datapath architectures with layout-accurate timing and area information. At its heart is the Motive timing evaluation technology from Viewlogic's Quad Design Group.

To complete Datapath, PathBlazer links to tools for logic synthesis, full-chip floorplanning and place-and-route. Links to Synopsys' Design Compiler enables non-datapath intensive design blocks.

The new verification methodology for ASIC sign-off uses the Chronologic Verilog Compiled Simulator (VCS), which includes ASIC sign-off support from vendors like LSI Logic, Toshiba and Lucent Technologies. To enable the timing-analysis sign-off methodology, Viewlogic added Motive and integrated the Sunrise TestGen testability engine to reduce verification time for sign-off by up to 80 percent.

Design functions are verified through functional simulation while timing is verified using Motive and high fault coverage through Test-Gen's automatic test pattern generation.

Viewlogic's ASIC Design-to-Test is an extension of the verification methodology, focusing on linking ASIC development tools and comprised of Chronologic VCS simulation, Quad Motive timing analysis and Sunrise TestGen test-automation tools.

Design-to-Test verifies test vectors with VCS, analyzes timing for delay path testing with Motive, and analyzes testability and synthesis with Sunrise Start tools. Test pattern generation is performed with Sunrise TestGen, and automatically prepared for vendor sign-off with VCS.

Viewlogic's Datapath Design Solution is available now to beta customers. The ASIC Design-to-Test and verification for ASIC sign-off products are commercially available now. Prices for the new offerings depend on configuration.

Under the Motorola/Viewlogic alliance, the companies will share strategic direction, tools, methodologies, and expertise to team Viewlogic's Silerity technology (PathBlazer datapath synthesis) with Motorola's advanced ASIC capabilities.

Also toward integrating technologies into comprehensive design flows, Viewlogic intends to support the Delay Calculation System, a suite of redefined data-format and tool-interoperability standards, jointly defined by Open Verilog International and the CAD Framework Initiative.

"Deep-submicron geometries, complex functional blocks and increasing device speeds wreak havoc on conventional ASIC design tool technologies and methodologies," said Will Herman, president and COO of Viewlogic. "Our long-standing leading-edge ASIC customer base gives us a clear view of what these designers need to realize the new generation of complex ASICs."

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