New EDA firms make waves

Electronic News,  May 6, 1996  by Judy Erkanat

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Los Altos/San Jose, Calif.--Two new companies emerged last week addressing aspects of high-performance IC design, with Frequency Technology in Los Altos and Simplex Solutions, Inc. in San Jose both planning to become prominent features on the electronic design automation (EDA) landscape.

Funded last June by Institutional Venture Partners, Frequency's founding team includes Martin G. Walker, president/CEO; K. J. Chang, VP of research; John Sliney, VP of marketing; Doug Kaufman, director of software architecture; and Andy Rappaport, consultant.

The company introduced its first product, Accurate True-3D Calibration services, based on proprietary technology and the expertise of its founding team. Future plans include combined, interworkable products and services, and, eventually, generalized products that work independently of its services.

Announcing its formal launch, Simplex is an EDA company focusing on deep-submicron semiconductor process technology. Organized and incorporated in April, 1995, by Resve Saleh, chairman; David Overhauser, VP of simulation product; and Shashank Goel, VP of verification products, the EDA start-up took in $2.5 million last July in its initial round of venture capital funding from the Mayfield Fund and a group of private investors, including Stanford University.

Simplex' founding team is a combination of academic forerunners and industry experts, including the recent addition of Synopsys executive Penny Herscher as president and CEO (EN, Antenna, April 29), and Kevin Walsh, VP of marketing.

"The depth and breadth of our collective experience in academia and the electronics industry equips us with a well-balanced and fresh perspective on both the theoretical nature of deep submicron design, as well as the practical needs of our prospective customers," said Dr. Saleh. "We have actively participated in relationships with IC designers struggling to cope with the myriad details of deep submicron technology, and are intimately familiar with the problems, issues, and challenges that it presents. Our inspiration and motivation to deliver broader, more elegant CAD solutions to designers emanates from the sense of urgency and heightened demand we observed during our thorough market analysis."

Besides its founders, Simplex also has the support of several well-known EDA names on its board of directors and technical advisory board. Company directors include Harvey Jones, chairman of Synopsys; A. Richard Newton, professor at the University of California, Berkeley; and F. Gibson (Gib) Myers, general partner of the Mayfield Fund. Technical advisory board members include Abbas El-Gamal of Stanford University; Chris Terman and Jacob White of the Massachusetts Institute of Technology; George Taylor of Exponential, Inc.; and Janak Patel of the University of Illinois.

"Semiconductor technology is outpacing all existing design and verification capabilities," continued Dr. Saleh. "Sub-0.5-micron processes enable us to build multi-million transistor devices, but today's CAD tools and methodologies are incapable of providing the capacity, accuracy, and speed to fully verify these complex IC designs. Furthermore, current point tool CAD products force designers to implement a disjointed, partial-chip verification methodology that requires numerous data conversions between tools. Simplex overcomes this verification bottleneck, with an innovative full-chip solution that streamlines the verification process and fits with the emerging post-layout, timing-driven methodology."

Simplex is developing a tightly integrated, easy-to-use commercial CAD software tool set accessing deep-submicron technology to mainstream IC designers. The company's products will address full-chip verification, covering functionality, performance, power, signal integrity, and reliability for chip designers and manufacturers in the microprocessor, application-specific standard product (ASSP) and ASIC markets.

Although Simplex doesn't plan its first product rollout until later in the month, Frequency unveiled its Accurate True-3D Calibration service aimed at spanning process and design development and addressing on-chip interconnect by bringing physics into the design flow facilitating interconnect extraction tools at the sub-half-micron level.

Frequency uses semiconductor fabrication process information and interconnect delay modeling to tune and calibrate a customer's existing extraction tools. Interconnect delay in sub-half-micron processes can effect chip performance by up to 50 percent. Currently, designers build guardbands into calculations to account for the impact of interconnect delays. By calibrating the tools to reality, a minimum amount of guardband can be identified so the design meets specification. With True-3D tools and data, a design converges with reality quickly and operates as required with a technology- and design-dependent guardband.

The True-3D calibration service evaluates and validates existing extraction tools using a True-3D perspective; gauges problem areas given specific designs and processes; calculates appropriate guardband schemes and optimizes rules files for extraction and delay calculators; and incorporates accurate data into existing design flow.