Viewlogic debuts high-level design tools

Electronic News,  Sept 19, 1994  

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MARLBORO, MASS. - Viewlogic Systems is introducing a new high-level design methodology for language-based design, which it calls Graphically Controlled Design, and a complement of new tools to go with it.

The three initial components of Graphically Controlled Design are ViewDesign Manager, ViewSchedule and two new synthesis packages, ViewSyn/FPGA and ViewSyn/ASIC. Viewlogic plans to bring out other tools in this line, including digital signal processing (DSP) design packages.

ViewDesign Manager is described as "a command and control center for the high-level design process." Designers can begin the process in a variety of ways, including block diagrams and language-based design. By pushing into a given block in the ViewDesign Manager block representation, the user automatically creates the next level of design hierarchy in a variety of forms: another block diagram, a textual description in VHDL, Verilog or ABEL; a graphical finite state machine diagram, a datapath diagram or an RTL or gate-level schematic. Next, the designer selects an appropriate Viewlogic point tool.

Three elements of ViewDesign Manager are the block diagram manager, hierarchy manager and project manager. Prices start at $10,000.

ViewSchedule is a new synthesis tool that generates digital designs from behavioral input. It is primarily aimed at synchronous clocked designs where several algorithms are being combined. It is also suitable for chips that have standard datapaths with embedded control, according to Viewlogic.

ViewSchedule was developed in conjunction with Abstract Hardware Ltd., the British software firm Viewlogic bought a minority equity interest in earlier this year (EN, May 16), and it uses formal manipulation technology embodied in Abstract's Lambda software. It offers computer-aided architectural alternatives that are "correct by construction," meaning each change in a design is managed and any changes that cause a violation of original design requirements are highlighted by the tool.

Interaction with ViewSchedule is through a graphical scheduling/resource editor. Output of the final architecture is in RTL-level VHDL, which can be synthesized by an architectural synthesis tool. ViewSchedule is priced at $39,500 and will be available in 1Q94.

ViewSyn/FPGA and ViewSyn/ASIC are new logic synthesis tools for designing field programmable gate arrays (FPGAs) and ASICs. They incorporate some synthesis technology acquired a year ago from Racal-Redac (EN, Oct. 18, 1993).

The Windows-based version of ViewSyn/FPGA is resold by Xilinx, Lattice Semiconductor, Intel, Motorola, Advanced Micro Devices and AT&T Microelectronics. ViewSyn/ASIC automatically creates design implementation, mapping into the most efficient cells available from a range of ASIC vendor libraries. Results are optimized to provide the minimum area design that meets speed objectives.

Both packages accept RTL, Verilog and VHDL design descriptions. They provide detailed reports on timing, constraints and area utilization, and they support the standard delay format (SDF) for delay back-annotation and the physical design exchange format (PDEF) for links to floorplanning and layout.

ViewSyn/FPGA is priced at $8,000 and $10,0000 under Viewlogic's Workview Plus and Powerview environments, respectively. ViewSyn/ASIC is $12,000 under Workview Plus and $15,000 under Powerview. Shipments begin in Q4 on Unix workstations and Windows-based PCs.

Viewlogic is also introducing HDL Designer, HDL Architect and HDL Expert for design based on the VHDL and Verilog hardware description languages. HDL Module, priced starting at $57,000, provides basic simulation and synthesis with traditional schematic entry. HDL Architect adds architectural synthesis and Motive timing analysis, at a base price of $84,000. The deluxe model for deep-submicron ASIC design is HDL Expert, priced starting at $195,000. Shipments begin in November.

"Viewlogic always strives to serve the design requirements of all classes of designers," said Alain J. Hanover, president and CEO of Viewlogic. "We have harnessed the incredible power of our array of high-performance, high-end tools for ASIC designers by encapsulating them in a unique graphical environment. At the same time, we have dramatically improved and expanded the capability of our own synthesis tools. And, in typical Viewlogic fashion, we made it affordable as well."

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