2001 Ad

Electronic News,  Dec 18, 2000  by Joerg Henkel,  Xiaobo Hu

• E-mail
• Print
• Link

The current state-of-the-art (mainstream) silicon technology deployed is based on 0.18-micron CMOS processes. From just a technology point of view, this enables the integration of hundreds of millions of transistors on a single piece of silicon. By 2005, a 0.10-micron process will theoretically be able to integrate more than 1 billion transistors on a chip (source: International Technology Roadmap for Semiconductors, 1999 Edition).

Practically, even nowadays, chips do not comprise the technology-enabled amount of transistors due to the often-discussed productivity design gap: the per-month designed amount of transistors per engineer grows at a slower pace than what new silicon processes enable. Core-based design methodologies try to overcome this bottleneck by building a system-on-a-chip (SOC) as a coimposition of predesigned/preverified cores such as a CPU or an MPEG decoder. Though core-based design is an efficient way, it solves only parts of the up-coming design problems since it mainly focuses on hardware design with few solutions for common hardware/software methodologies.

In order to explain this point, we have to give an insight into what is most likely a future trend. There are strong indications, from places such as the technology roadmap at 2010, that mask-layouts of deep-submicron designs (0.10 micron and beyond) are becoming so expensive that a mask-layout of a billion-transistor chip cannot be manufactured for one type of device only.

In other words, there will be one SOC for a whole family or class of devices. Such an SOC features a huge functionality that is most likely not used by a single application. This is only one of the points where the interplay of software and hardware becomes essential. The software has to make sure that nonused or temporarily nonused SOC parts (cores) are correctly configured and/or shut down in order to guarantee efficient functionality according to the required design constraints for a specific application.

This might change the way EDA tools are deployed. Rather than designing and optimizing for an application before implementation, we could see built-in EDA tools that analyze an application when already implemented and running, and then adapt the surrounding generic hardware architecture around by configuring system parameters. Recent research approaches confirm this trend (see publication by Vahid et al. at the CASES 2000 conference).

At least equally important is the test and verification domain. Major breakthroughs in the mid-1990s have established formal verification techniques as a powerful means to partly replace traditional test strategies. The importance is due to predictions that in a couple of years the test costs per transistor will exceed the production costs. It can be observed, however, that test is mainly focused on either hardware or software. A significant amount of research work has to be focused toward combined hardware/software test strategies in order to verify future systems with the complexity and functionality as described above.