War erupts in FPGA design: Cadence, Synopsys mount separate campaigns targeted at taking on Mentor Graphics - Exclusive

Electronic News,  June 17, 2002  by Gale Morrison

Tags: Cadence Design Systems Inc., FPGA, Mentor Graphics Corp.

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No.1 and No.2 EDA vendors Cadence and Synopsys are preparing huge pushes into advanced FPGA design this fall, and No.3 player Mentor Graphics has pledged not give an inch in the space it leads, having beat Cadence and Synopsys at this game a few times already.

Cadence has just signed an OEM deal--which in the software world means Cadence will integrate and market another company's software--with Translogic's of the Netherlands for its EASE graphical HDL entry tool, Electronic News has learned.

Cadence's NC-Sim HDL simulator is said to be the linchpin of the upcoming FPGA strategy, and Translogic's EASE would be the entry point for such a flow. Translogic's largest customer is Ericsson, a huge user of Cadence tools of all kinds.

CEO Ray Bingham confirmed the plan and pledged to say more in September. As a preface, he described the strategy as a trilateral power play by Cadence, IBM Microelectronics and Xilinx, which would fit neatly into plans by all three companies to suit Cisco Systems at every design and silicon turn. IBM has been serving Cisco in ASIC design and manufacturing since Cisco purchased IBM's net working hardware division in 1999. Last fall, Xilinx signed a $100 million deal with IBM for high-end manufacturing. It also signed a five-year joint development deal with Cadence, about which there hasn't been much detail--until now.

Synopsys Chairman and CEO Aart de Geus also confirmed there would be a major launch this fall, indicating the Synopsys plan is similar to Cadence's in its focus on the HDL simulator. He also acknowledged Synopsys has had difficulty fulfilling its vision of conquering FPGA design.

"This is an area we have not been as successful in," said de Geus of the company's FPGA Express line. "We're working on a major revamp of that, and we've got new technology in the pipeline that will specifically connect well to our existing tools." Included in that technology will be the company's VCS simulator, which Synopsys just launched in version 7.0.

Mentor Graphics' commanding 45 percent share of the FPGA tools market is due in no small part to its ModelSim product, which it acquired a few years ago when it bought Model Technology Inc. It picked up its synthesis technology when it bought Exemplar Logic at about the same time. Mentor has continued to build momentum, especially since it folded it all under the Mentor HDL division banner.

Wheeling and Dealing

Cadence apparently also has gotten designs on the synthesis piece of a new FPGA design flow. The company has been trying to buy FPGA synthesis player Synplicity, but its most recent offer was rebuffed by Ken McElvain, Synplicity's founder and CTO.

Bingham said he had no comment about the offer. Meanwhile, Synplicity said it does not comment on rumors.

A source familiar with the FPGA market said McElvain is fighting acquisition because he wants to fulfil his vision of hitting the big time by broadening into ASIC synthesis, as the company's most recent products have been meant to do. But Silicon Valley is littered with engineering founders who fought the board and then had their technologies ripped from their arms, the source commented. While McElvain may have veto power on the offer, the power resides with Synplicity Chairman and CEO Bernie Aronson, who brought the company to IPO last fall.

The backdrop to all this activity is the high-growth potential for FPGA designs as the programmable logic gets much, much bigger and more capable--with specs such as 10 million equivalent gates and loads of memory and pre-engineering CPU and DSP cores. In fact, Xilinx is announcing the shipment of its Virtex II Pro line today, and Altera is doing the same for its Stratix devices.

These kinds of FPGAs are currying much more favor with communications designers who can't face $1 million ASIC mask costs and don't have concrete communications protocols to work with.

The Road Out of System C

One of hottest stories emerging last week from the Design Automation Conference (DAC) in New Orleans -- not least because it's a critical technology that has been brought about with only $2.3 million in venture funding so it could be bought up on the cheap -- was AccelChip. The Chicago-area company has perfected the software to take DSP designs in their de facto standard Matlab programming language format and generate the equivalent HDL to map into an FPGA.

This has broader implications than just packages of FPGA design tools, and AccelChip CTO Prith Banerjee explained why.

"All DSP specs are written in Matlab, and these guys absolutely do not want to move from it. They tell us they are sick to death of Cadence and Synopsys coming in to tell them about SystemC. Matlab is easier, more intuitive and involves 10 to 20 times less code," Banerjee said. "Matlab and C, like SystemC, will coexist, but we strongly believe this will be successful."

AccelChip already has a joint development program with smaller FPGA house QuickLogic and counts Motorola as a customer.