Chinese DRAM maker ChangXin Memory Technologies, or CXMT, says its fifth-generation G5 manufacturing platform has entered mass production, alongside two 24-gigabit LPDDR5X memory products built on it. The announcement, made at the World Manufacturing Convention in Hefei and reported September 20, is a significant public milestone for a company trying to broaden China’s domestic supply of advanced memory chips.
The products are aimed at smartphones and other portable devices, a market where LPDDR5X is used as short-term working memory for applications and operating systems. Reuters reporting said CXMT described the G5 platform as in mass production; China Daily separately reported the same status and said the two 24Gb chips had entered volume production. The reports establish the announcement and its stated specifications, but they do not provide independently audited output, defect rates, customer volumes or performance comparisons with the largest international memory suppliers.
What CXMT has announced
CXMT said G5 uses quadruple patterning, a lithography approach that creates features through several patterning and etching steps rather than relying on a single exposure. It reported an active-area half-pitch of 11.95 nanometres in the DRAM array. In memory manufacturing, half-pitch describes the spacing associated with repeating structures in a specified portion of the chip, here the array that stores data.
That number should not be read as an 11.95nm logic-chip process node. Logic-node labels used for processors are commercial and technical descriptions tied to different transistor structures and design rules; a DRAM array measurement captures only one relevant dimension of a memory process. It nevertheless offers a concrete indication of the kind of feature scaling CXMT says it has achieved.
The company also said G5 can produce at least 50% more gross dies per wafer than its fourth-generation platform, calculated on an 8Gb-equivalent basis. Gross dies are the chips physically patterned on a wafer before testing excludes defective units. The figure therefore describes potential die density, not a 50% improvement in manufacturing yield or a guarantee of 50% more sellable chips. Actual usable output depends on defect density, binning and the proportion of wafers that meet product specifications.
Higher density, but limited independent evidence
The two announced products each carry 24 gigabits of LPDDR5X memory, a capacity relevant to handset makers that want more memory in a limited physical footprint. CXMT vice president Luo Xiaodong said the chips had entered mainstream domestic flagship smartphones, according to China Daily, but the company did not identify handset brands or models. Reuters characterized the products as being offered for smartphones and portable devices.
Luo also said the process capability was comparable with the most advanced mass-produced nodes in the industry. That is a company assertion, not an independently demonstrated ranking. Neither report included comparative electrical performance, power-consumption data, reliability results, wafer-start volumes or a breakdown of yields that would allow outside analysts to assess how G5 compares with products from Samsung Electronics, SK Hynix or Micron Technology.
Those omissions are common in semiconductor announcements, particularly for memory, where the commercial value of a process depends on more than minimum feature dimensions. Customers also assess supply continuity, qualification history, power characteristics, controller compatibility and the manufacturer’s ability to deliver large volumes consistently. A 24Gb LPDDR5X die can be a meaningful product step without settling the broader question of competitiveness across those measures.
Why multipatterning is part of the story
Quadruple patterning can help a chipmaker form denser structures using lithography equipment that may not match the most advanced tools available elsewhere. The trade-off is complexity: each extra patterning stage adds alignment, deposition, etching and inspection work, creating more opportunities for defects and raising process-control demands. CXMT said it developed G5 through computer simulations and collaboration with Chinese equipment makers on critical production steps, according to Reuters.
The manufacturing route also has policy significance. U.S. export controls have increasingly targeted advanced semiconductor equipment and technology. A CSIS analysis of the updated U.S. controls notes restrictions affecting certain equipment for advanced DRAM production and provisions aimed at limiting technology that could support advanced memory, including high-bandwidth memory. The rules do not by themselves show what equipment CXMT used for G5, but they explain why a domestic process built around difficult multipatterning steps attracts attention.
CXMT’s announcement follows a shorter but visible product timeline. The company officially debuted a DDR5 portfolio in November 2025, with 16Gb and 24Gb dies directed at servers, workstations and PCs, according to industry reporting in May. G5 shifts the public emphasis to LPDDR5X, a low-power memory category central to mobile devices, and to an asserted new manufacturing platform rather than a product rollout based on previously disclosed generation technology.
For now, the most solid conclusion is narrower than CXMT’s broader competitive claim: the company has publicly put a higher-density LPDDR5X platform into its stated mass-production phase and disclosed a specific array measurement and die-density comparison. Whether it can convert that platform into sustained, high-yield supply for named phone makers will be measured in qualification wins and shipment volumes that have not yet been disclosed.