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Industry: Email Alert RSS FeedSix Generations of SCSI Working Together - interface technology - Technology Tutorial
Computer Technology Review, Sept, 1999 by Paul D. Aloisi
This article is the first in a two-part series. The second part will appear in the October Issue of CTR.
SCSI is a work in progress. There are six generations of SCSI currently on the market. This interface technology started with asynchronous communications up to 5MB/sec over a 50-conductor cable. The large 50 pin connector in SCSI-1 has shrunk to a 68 pin VHDCI connector and the data rates increased to 160MB/sec. SCSI development has followed Moore's law with speed doubling about every two years. There are two more generations planned for LVD SCSI, Fast-160 (320MB/sec) and Fast-320 (640MB/sec).
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During start up, the SCSI controller sends an inquire command for each devices' capability. Each device is set to the maximum performance that the controller and the device being accessed can operate. This allows each device to perform at its capability on the same SCSI bus or maintaining legacy compatibility, working with several generations of SCSI.
The SCSI bus has three different electrical interfaces, single-ended (SE) with a ground return line, High Voltage Differential (I-LVD) SCSI, and Low Voltage Differential (LVD) SCSI. Single-ended was the original interface and can be used for speeds up to Fast-20 (Ultra) SCSI. The maximum performance on a wide bus is 40MB/sec. HVD SCSI was called just differential SCSI for many years. It was based on EIA485 and required special high voltage, high-speed transceivers to handle the power. The HVD SCSI 9 line transceiver dissipates 1 watt when it is enabled because of the high voltage driven on the line. LVD SCSI was introduced in SCSI Parallel Interface-2 (SPI-2) for Fast-40 (Ultra2 SCSI) and beyond it can be used for the slower speeds. The LVD SCSI 27 line controller with integrated dissipates just over a watt when the transceivers are enabled and driving the bus.
SCSI-1 is often lumped together with SCSI-2 as a basic starting level. SCSI-1 only allowed Asynchronous transfers where each byte transferred was acknowledged, the control lines and low data byte and parity line is passed through a 50-pin cable. SCSI-2 allowed for synchronous transfers, which count the number of transfers for the message. SCSI-3 split the standard into the physical layer, primary commands, and protocol command sets. The Parallel interface document for SCSI-3 is SPI (SCSI Parallel Interface). SPI made the wide SCSI bus practical by adding a single 68-pin P cable. Fast-20 was a separate document that just addressed a speed increase to SPI, doubling the transfer rate to 20megatransfers/sec. SPI-2 added the LVD SCSI and the transfer rate to Fast-40 speed. SPI-3 doubles the speed again by adding double edge clocking. SPI-3 also added: CRC, Domain Validation, Packetized and QAS (Quick Arbitration and Selection.)
The SCSI bus termination provides the negation of the signal when no driver is actively driving the bus and provides an impedance match. SCSI buses must be terminated at each end of the bus; there should be no termination enabled in the middle of the bus, only the end devices. SCSI bus transitions from wide to narrow; the high byte and parity should be terminated at the transition point.
The Same Electrical Interface Systems
Many systems need to have multiple generations of SCSI attached, some examples are Wide Ultra and Fast Wide SCSI high speed disks operating with CD-ROMs, CD-R, CD-RW, tape drives, removable media, and scanners that are Fast SCSI. This is the same electrical interface with different bus widths and performance levels operating on the same physical bus.
The transition point between the wide and the narrow bus must terminate the high data byte and Parity one line (Fig 1). Mixing bus widths can be a major problem if there are too many narrow devices attached to the bus. The loading will be higher on the control and low byte data lines, causing signal SKEW. The high byte data will arrive before the clock and may be changing to the next data transfer when the clock arrives, causing data errors. Let's think about the pin out of a Multimode (LVD/MSE) 68 pin to 50-pin adapter. For a single ended only version, the Positive signal lines become ground returns and the Diff Sense line becomes a ground line. In general, if there are more than two narrow devices attached to a bus with wide devices, either separate the buses with a separate adapter or an expander or compensate for the difference in loading by adding 20 pF per narrow device to each high byte data and parity lines.
The host adapter controller ID is normally 7, the narrow bus devices can use ID 0-6, and the wide bus devices can use ID 0-6 and 8-15. ID 7 is the highest priority and then 0-6 where 0 is the highest, and 8-15 where 8 is the highest priority of this group.
With adapters that have 50 pin and 68 pin internal connector ports and an external 68-pin connector, only two of the connectors can be used at any time. If all three connectors are used, it will create a bus tee where one of the buses would appear as a lumped load, If one of the 68 pin connectors is used with the 50-pin connector, the adapters normally automatically terminate the high byte.